1. Field of the Invention
The present invention relates to packaging substrates, semiconductor packages and fabrication methods thereof, and, more particularly, to a carrier-free packaging substrate, a semiconductor package and a fabrication method thereof.
2. Description of Related Art
A conventional packaging substrate has a core board and build-up structures symmetrically formed on both sides of the core board. The use of the core board increases the length of the conductive path and the thickness of the overall structure, thus hindering miniaturization of electronic products. Accordingly, coreless packaging substrates are provided to shorten the conductive path and reduce the thickness of the overall structure so as to meet high frequency and miniaturization requirements.
FIGS. 1A to 1L are schematic cross-sectional views showing a conventional coreless packaging substrate and a fabrication method thereof.
Referring to FIG. 1A, a carrier 10 having a first surface 10a and a second surface 10b opposite to the first surface 10a is provided.
Referring to FIG. 1B, a first conductive layer 11a and a second conductive layer 11b are formed on the first surface 10a and the second surface 10b, respectively.
Referring to FIG. 1C, a first resist layer 12 is formed on the first conductive layer 11a and has a plurality of openings 120 for exposing portions of the first conductive layer 11a. 
Referring to FIG. 1D, a first metal layer 13 is formed in the openings 120 of the first resist layer 12 by electroplating.
Referring to FIG. 1E, a second resist layer 14 is formed on the first resist layer 12 and the first metal layer 13 and has a plurality of openings 140 for exposing portions of the first metal layer 13.
Referring to FIG. 1F, a second metal layer 15 is formed in the openings 140 of the second resist layer 14 by electroplating.
Referring to FIG. 1G the first resist layer 12 and the second resist layer 14 are removed.
Referring to FIG. 1H, an encapsulant 16 is formed on the first conductive layer 11a for encapsulating the first metal layer 13 and the second metal layer 15.
Referring to FIG. 1I, the encapsulant 16 is partially removed so as to be flush with the second metal layer 15.
Referring to FIG. 1J, a third resist layer 17 is formed on the second conductive layer 11b and has a cavity 170 for exposing a portion of the second conductive layer 11b. 
Referring to FIG. 1K, the exposed portion of the second conductive layer 11b and the carrier 10 and the first conductive layer 11a under the second conductive layer 11b are removed.
Referring to FIG. 1L, the third resist layer 17 is removed and a surface finish 18 is formed on surfaces of the first metal layer 13 and the second metal layer 15.
Although having a small thickness, the above-described coreless packaging substrate still requires two electroplating processes, thus resulting in a high fabrication cost.
FIG. 2 is a schematic cross-sectional view showing a carrier-free semiconductor package 2 as disclosed by U.S. Patent Application Publication No. 2012/0007234. A plurality of grooves 200 and a plurality of conductive pillars 201 corresponding to the grooves 200 are formed in a metal carrier by etching. Each of the conductive pillars 201 corresponds in position to an electrical terminal or a chip pad. The grooves 200 are filled with an encapsulant 21. The semiconductor package 2 dispenses with two electroplating processes to thereby save the fabrication cost.
However, since the inner portion of each of the conductive pillars 201 has a bell shape due to the etching process, after a thermal cycling test, the encapsulant 21 can easily crack and the conductive pillars 201 can easily fall off from the semiconductor package 2.
Therefore, how to overcome the above-described drawbacks has become critical.